High-performance FPGA packet-routing codebase for heavy-lift launch vehicle second stage application.

Packet-Routing FPGA Codebase for Heavy-Lift Launch Vehicle Second Stage

High-performance FPGA packet-routing codebase for heavy-lift launch vehicle second stage application.

Developed and optimized FPGA components for heavy-lift launch vehicle packet routing, enhancing design, simulation, and debugging within an Agile engineering environment.

An aerospace client engaged ALTEN Technology to provide a team of up to five FPGA engineers, integrating seamlessly into their Agile development process to create critical packet-routing FPGA components for the second stage of a heavy-lift launch vehicle. Operating within the client’s system, the ALTEN Technology team extensively utilized Avalon and AXI protocols and helped refine the client’s internal processes. Their efforts resulted in the development of large portions of the FPGA routing pipeline, efficient adaptation to the client’s extensive IP library, and successful debugging of existing issues in previously generated IP. The project involved the comprehensive design, implementation, modeling, and simulation of functionalities such as packet routing, IPv4, UDP, DDR3, LVDS, and Ethernet, with all designs modeled in MATLAB and simulations meticulously crafted in ModelSim and Questasim.

Packet-Routing FPGA Codebase for Heavy-Lift Launch Vehicle Second Stage

Packet-Routing FPGA Codebase for Heavy-Lift Launch Vehicle Second Stage